The microelectronic industry is continually striving to produce ever faster and smaller microelectronic packages for use in various electronic products, including, but not limited to, computer server products and portable products, such as portable computers, electronic tablets, cellular phones, digital cameras, and the like. As these goals are achieved, the fabrication of the microelectronic packages becomes more challenging.
Microelectronic packages generally include at least one microelectronic die attached to a microelectronic substrate, such as an interposer. Microelectronic substrates are generally composed of alternating layers of dielectric material (such as organic materials) and metal (such as copper) which is patterned to form conductive routes. The microelectronic die, such as a silicon die having integrated circuitry formed therein, may be physically and electrically attached to the microelectronic substrate, such that the conductive routes in the microelectronic substrate direct electronic signals to and from the integrated circuitry of the microelectronic die. However, the components of the microelectronic package have differing coefficients of thermal expansion. For example, at room temperature (e.g. about 25° C.), an organic dielectric material, such as a silica-filled epoxy (such as materials available from Ajinomoto Fine-Techno Co., Inc., 1-2 Suzuki-cho, Kawasaki-ku, Kawasaki-shi, 210-0801, Japan (e.g. Ajinomoto ABF GX-92)), has a coefficient of thermal expansion of about 39 ppm/° C., a metal for the conductive routes, such as copper, has a coefficient of thermal expansion of about 17 ppm/° C., and a microelectronic die, such as silicon, has a coefficient of thermal expansion of about 2.6 ppm/° C. The fundamental differences in the thermal expansion of these components may result in temperature dependent deformation or warpage of the microelectronic package. This warpage may cause significant issues during the attachment of the microelectronic package to external substrates, such non-wet opens and solder bump bridging. This warpage can be mitigated by utilizing a thick “core” material at the center of the microelectronic substrate. This core material generally has a high glass transition temperate and a low coefficient of thermal expansion, which lowers the composite coefficient of thermal expansion of the microelectronic substrate. However, the core material coefficient of thermal expansion has already been reduced below 4 ppm/° C. and is becoming increasingly difficult to reduce further. Additionally, there is significant demand to reduce the total height or thickness of microelectronic packages. Much of this reduction is achieved by thinning the core material, in turn, giving the core material less influence on warpage. Given these factors, it is important to develop new warpage control methodologies, especially for height/thickness constrained microelectronic packages, such as those used in cellular phones and electronic tablets.